1. Field of the Invention
The present invention relates to a method of forming a hole pattern. The present invention in particular relates to a method of forming a hole pattern to be used in a fine wiring pattern of a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-263401, filed Oct. 9, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
The mainstream of microfabrication technology of a semiconductor device is currently photolithography. By means of photolithography, fine hole patterns are formed and semiconductor devices are manufactured.
A hole pattern is a pattern which consists of a recessed portion or groove portion that is formed in an interlayer insulation film prepared on a semiconductor substrate. A hole pattern is formed in various shapes, such as a line shape or L shape or the like when viewed from above. Such a hole pattern can be used for a fine wiring pattern or the like of a semiconductor device.
In recent years, along with the increasing density and increasing integration of semiconductor devices, the need is increasing to form hole patterns consisting of dimensions below the resolution limit of photolithography technology to be used for fine wiring patterns. A number of methods have been proposed to form a hole pattern consisting of dimensions below the resolution limit of photolithography by adding some kind of technology to photolithography in order to meet such a need.
For example, technologies to form such a hole pattern include silicon film hard mask technology that has a sidewall of silicon, RELACS (resolution enhancement lithography assisted by chemical shrink) technology, and resist thermal flow technology.
(Silicon Hard Mask Technology Having a Silicon Sidewall)
A description of this technology shall be given with reference to FIGS. 2A to 2I.
First, as shown in FIG. 2A, for example an interlayer insulation film 202 is formed as an object to be processed on an upper surface 201a of a semiconductor substrate 201. A first silicon film 203 is formed by the LP-CVD (low-pressure chemical vapor deposition) method on an upper surface 202a of the interlayer insulation film 202.
Next, as shown in FIG. 2B, a photoresist layer 204 is formed on an upper surface 203a of the first silicon film 203. Furthermore, as shown in FIG. 2C, a photoresist layer 204 is patterned using a well known lithography technology.
Next, as shown in FIG. 2D, dry etching of the first silicon film 203 is carried out using the photoresist layer 204 as a mask to transfer the pattern of the photoresist layer 204 to the first silicon film 203. Then, the photoresist layer 204 is removed by ashing, and as shown in FIG. 2E, a hole pattern 250 of width W is formed in the first silicon film 203.
Next, as shown in FIG. 2F, a second silicon film 205 is formed to a desired film thickness using the LP-CVD method.
Moreover, as shown in FIG. 2G, etch back is carried out on the silicon film 205 using a well known dry etching technology to leave the second silicon film 205 in the shape of a sidewall on a sidewall surface 203c of the first silicon film 203.
Next, as shown in FIG. 2H, dry etching is performed on the interlayer insulation film 202 with the first silicon film 203 and the second silicon film 205 serving as a hard mask to form a hole pattern 255 of width w (w<W).
Next, as shown in FIG. 2I, the first silicon film 203 and the second silicon film 205 that were used for the hard mask are removed by etching. By doing so, the hole pattern 255 of width w (w<W) is formed in the interlayer insulation film 202.
If the above technology is used, by suitably setting the film thickness of the second silicon film, 205, it is possible to control the width of a hole pattern by the dimension which cannot be formed only with the existing lithography technology.
However, there are issues in this technology of using the first silicon film 203 and the second silicon film 205 for a hard mask. That is, when using the first silicon film 203 and the second silicon film 205 as a mask and etching an oxide film (interlayer insulation film 202), the etching selection ratio cannot be made high. For this reason, it is necessary to set the first silicon film 203 to be thick. As a result, it is unavoidable to also increase the film thickness of the photoresist layer 204 that is used for the mask for patterning the first silicon film 203. However, there are the problems of the photoresist layer 204 with a thick film thickness being hard to resolve and difficult to detail.
Also, time is required for etching the thick silicon films 203, 205, and achieving a practical throughput is difficult. Since unlike the photoresist layer 204, the first silicon film 203 and the second silicon film 205 cannot be readily removed, it is necessary to perform etching removal of the first silicon film 203 and the second silicon film 205 by dry etching, and in that case there is the risk of etching away a portion of the semiconductor substrate 201 that should not be etched.
(RELACS Technology)
Next, RELACS technology shall be described. In RELACS technology, a crosslinking reaction of a polymer is allowed to take place only on the upper surface of a photoresist layer by an acid that is contained in a chemical-sensitization resist. Thereby, RELACS technology controls the dimension of the hole pattern of a photoresist layer, enabling a reduction in the hole pattern width. For example, this technology is disclosed in p. 507 to p. 510 of “Advanced RLACS Technology for ArF Resist” by Mamoru Terai, Toshiyuki Toyoshima, Takeo Ishibashi, Shinji Tarutani, Kiyohisa Takahashi, Yusuke Takano, and Hatsuyuki Tanaka in Journal of Photopolymer Science and Technology, Volume 16, Number 4, (2003).
Moreover, as the hard mask that is used in this technology, a carbon film layer is used that is formed by the PE-CVD (Plasma Enhanced CVD) method and easily removable by ashing. As the carbon film layer, for example, APF (Advanced Patterning Film) of Applied Materials Inc., AHM (Ashable Hard Mask) by Novellus Systems Inc., NCP (Nano Carbon Polymer) by ASM or the like may be used.
Hereinbelow, the description is given using FIGS. 3A to 3F for the dimension control technology that used the RELACS technology with a carbon film layer serving as the hard mask.
First, an interlayer insulation film 302 is formed on an upper surface 301a of a semiconductor substrate 301. A carbon film layer 303 is formed with the PE-CVD or the like on an upper surface 302a of the interlayer insulation film 302. Furthermore, an intermediate mask layer 304 which consists of an oxide film is formed on an upper surface 303a of the carbon film layer 303. After applying a photoresist layer 305 on the intermediate mask layer 304, as shown in FIG. 3A, a hole pattern 350 of width W is formed in the photoresist layer 305 using a well known lithography technology.
Next, as shown in FIG. 3B, a RELACS polymer 306 is formed using the RELACS technology on an upper surface 305a and a sidewall surface 305c of the photoresist layer 305.
Next, as shown in FIG. 3C, dry etching of the intermediate mask layer 304 is carried out using the RELACS polymer 306 and the photoresist layer 305 as a mask, and a hole pattern 355 of width w (w<W) is formed.
Next, as shown in FIG. 39, dry etching of the carbon film layer 303 is carried out using the intermediate mask layer 304 that has been patterned as a mask. At this time if the photoresist layer 305 is set to be thinner than the carbon film layer 303, the photoresist layer 305 and the RELACS polymer 306 are automatically removed.
Next, as shown in FIG. 3A, dry etching of the interlayer insulation film 302 is carried out using the carbon film layer 303 that has been patterned as a mask. At this time, the intermediate mask layer 304 is automatically removed by etching.
Finally, as shown in FIG. 3B, the carbon film layer 303 is removed by an oxygen plasma ashing process. By doing so, the hole pattern 355 of width w (w<W) is formed in the interlayer insulation film 302.
This method has a number of advantages compared to the technology that uses a silicon film as a hard mask as described above. For example, since the photoresist layer 305 should withstand patterning of the intermediate mask layer 304, it is possible to make the film thickness of the photoresist layer 305 comparatively thin, which has the advantage of being readily microfabricated, Also, the RELACS polymer 306 that is used for controlling the dimension can be removed simultaneously with the photoresist layer 305. In this way, although the steps appear at first to be complex, due to such reasons as each layer being automatically removed, the number of steps is held down.
However, in this RELACS process, the acid in the resist is insufficient when forming a fine pattern. For this reason, a hole pattern dependency occurs in the film thickness of the RELACS polymer 306 that is formed. Also, the acid reactivity in the photoresist layer 30 falls after patterning due to a minute amount of ammonia in the atmosphere. For this reason, there is also the issue of highly accurate film thickness control being difficult.
(Photoresist Layer Thermal Flow Technology)
Next, photoresist layer thermal flow technology shall be described. This technology is disclosed in “Forming sub-100 nm contact holes” by Takamitsu Furukawa, Norio Moriyama, Kazuo Sawai, and Hiroshi Onoda in OKI Technical Review, April 2002/Issue 190 Vol. 69 No. 2, pp. 58-61. This technology is a process that actively utilizes a thermal flow in a patterned photoresist.
First, as shown in FIG. 4A, a hole pattern 450 is formed in a photoresist layer 405. Then, a thermal process is performed to generate a thermal flow in the photoresist layer 405 in the direction of the arrows shown in FIG. 4B, and the hole pattern 450 of width W is made into a hole pattern 455 of width w (w<W). Then, the hole pattern 455 of width w is finally formed in the interlayer insulation film 402 similarly to the method disclosed above.
In this method, there is a tendency for the thermal flow to depend on the size and shape of the hole pattern 450. For this reason, there is the risk of dimensional differences occurring due to the density and shape of the hole pattern 450.
As another conventional technology, Japanese Unexamined Patent Application, First Publication No. 2007-027180 discloses a method of manufacturing a semiconductor device capable of easily forming a high aspect ratio fine contact hole with good controllability.
This method is a manufacturing method of a semiconductor device for forming an opening in an insulation film that is an object to be processed. This manufacturing method includes following steps: a step of forming an insulation film on a substrate, a step of forming a hole pattern consisting of a first etching mask (photoresist layer) on the insulation film, a step of forming a first hole by making an etching opening midway in this insulation film with this hole pattern serving as a mask, a step of forming a second etching mask (carbon film layer formed by the CVD method) on the top portion of the insulation film and in a sidewall shape on the sidewall of the first hole that is opened midway after removing the first etching mask, and a step of etching the insulation film that remains at a lower portion to form a second hole with the second etching mask serving as a mask.
But, in this method, in order to open a small pore (the second hole), a large pore (the first hole) must be formed first. For that reason, a step in the pore diameter ends up being formed, and so the problem arises of its applications being limited.
This patent document also discloses a method including following steps: a step of forming an insulation film such as a nitride film on a film of the object to be processed, separately from the insulation film that is the object to be processed, a step of forming a first hole in this insulation film, and a step of selectively removing the nitride film by heated phosphoric acid after forming a second hole. This method also cannot be used in the case of metal wiring or the like being under a hole, and so the problem arises of its applications being limited.
In this patent document, the second etching mask that is formed on the sidewall of the first hole is envisaged as a carbon film layer. In a semiconductor process, a carbon film layer formation technology includes the PE-CVD method and the LP-CVD method. Although the PE-CVD method enables film formation at a low temperature (around 400° C.), the step coverage is poor, and so it is unsuitable for stringent dimension control that is required for forming a hole pattern of 60 nm or less. The LP-CVD method can form a carbon film layer with good coverage if ethylene gas is used, but requires a high temperature of around 800° C., and so the problem arises of its applications being limited.
Japanese Unexamined Patent Application, First Publication No. H09-045633 discloses a method of forming a fine contact hole of a semiconductor integrated circuit. This forming method includes following steps: a step of forming a carbon thin film on an insulation film that is the object to be processed, a step of forming a photoresist layer thin film on the carbon thin film, a step of patterning the photoresist layer thin film by photolithography, a step of etching the carbon thin film into a normal tapered shape with the photoresist layer thin film serving as a mask, and a step of etching the insulation film that becomes the work target object with the patterned carbon film layer and the photoresist layer thin film serving as a mask. That is, by patterning the carbon film layer into a normal tapered shape by the photoresist layer that is a similar carbon-based film, the hole diameter is narrowed, and a small hole is formed.
But, in this method, the selection ratio cannot be made high during etching of the carbon film layer since etching of the carbon-based film is performed using a similar carbon-based film as a mask. For that reason, the photoresist layer must have a thickness equal to or greater than the carbon film layer.
Moreover, the film thickness of the carbon film layer depends on the film thickness of the insulation film that is the work target and the etching conditions. Thereby, if the film thickness of the insulation film that is the work target differs, the need arises to change not only the film thickness of the carbon film layer but also the film thickness of the photoresist layer. However, in the current fine processing, the film thickness of the photoresist layer is optically optimized in order to avoid such effects as a stationary wave effect due to reflection of light, and so arbitrarily setting the film thickness is difficult.
Furthermore, if the film thickness of the carbon film layer changes, the condition for processing the carbon film layer into a normal tapered shape must also change.
In this manner, mutually dependent parameters become intricately entwined, and so just by changing the film thickness, the problem arises of the optimization becoming extremely difficult.
Japanese Unexamined Patent Application, First Publication No. H11-261025 discloses a method including following steps: a step of for g a first insulation film and a second insulation film that are work targets on a semiconductor substrate, a step of forming a photoresist layer pattern that serves as a mask on the second insulation film, a step of forming a hole in the second insulation film by etching using the photoresist layer pattern as a mask, a step of narrowing the hole diameter by for g a sidewall that contains a component of the photoresist on the sidewall of the hole in a reaction chamber of an etching apparatus, and a step of forming a hole in the first insulation film by etching with the photoresist layer and the sidewall serving as a mask.
This technology resembles the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-027180 mentioned above. However) it differs on the point of the formation of a sidewall (carbon-based film) that consists of a component of the photoresist layer for obtaining a small hole diameter being conducted in a reaction chamber of an etching apparatus.
The formation of the carbon film layer, which is performed in succession to processing of the second insulation film by etching, depends on the history of the etching chamber. For this reason, the etching conditions of the second insulation film affect the formation of a carbon-based film. Also, the problem arises of the thickness of the sidewall easily changing due to the denseness/sparseness of the hole pattern.
Accordingly, there are the problems of independently controlling the etching conditions of the second insulation film and the formation of the carbon-based film being difficult, and lacking the strict dimension controllability required for the device manufacture of 60 nm onward.